1. Field of the Invention
This invention relates generally to the integrated structure and configuration of capacitors, together with resistors and/or inductors, and more particularly to an improved structure and arrangement of capacitors, together with resistors and/or inductors formed on semiconductor substrates using digital CMOS semiconductor processing techniques.
2. Background Art
In the formation of integrated circuits on semiconductor substrates, such as in the manufacture of microprocessors and ASIC (Application Specific Integrated circuit) chips, various devices and circuit components are formed and connected by surface or internal wiring to form desired circuits. Among the components that are formed are capacitors and resistors. These components are used in many different circuits in many different ways. However, as device sizes and the circuit sizes decrease, and the number of devices that can be formed on the various substrates increases it is increasingly difficult to retain enough surface area or "real estate" to form resistors or inductors, or other similar type components, which take up relatively large areas, as opposed to the areas required for the logic devices such as transistors, diodes, and the like. Moreover, formation of capacitors using essentially FET (field effect transistor) technology utilizes a substantial amount of surface area or "real estate".
Thus it would be desirable to be able to use FET technology to form capacitors and also form resistors and/or inductors using a minimum of surface area or "real estate" in the final product. For high frequency applications, the capacitor is segmented into multiple polysilicon strips. In this case, FET channel length is reduced; therefore, FET channel resistance is reduced, and thus the segmented capacitor time constant is reduced.